1. Technical Field
This disclosure is directed to electronic circuits, and more particularly, to circuits used for generating clock signals.
2. Description of the Related Art
Many integrated circuits (ICs) have clock generation circuits implemented thereon. The clock circuits may be used to generate clock signals that are provided to various clocked circuits, such as synchronous logic circuits implemented on the corresponding IC.
One common type of clock generation circuit is the phase locked loop (PLL). A PLL is a feedback-based system in which a phase difference between a reference signal and a feedback signal. A typical PLL includes a phase detector, a low pass filter, an oscillator, and a feedback path. Some PLLs may have additional circuitry, such as multipliers, dividers, and so forth.
In some cases, portions of an IC in which a PLL is implemented may be placed in a low-power mode, such as a sleep mode, in which idle circuitry is powered down. In some cases, portions of the PLL may also be powered down. When exiting the low-power mode, the PLL may re-lock to the frequency at which it was locked prior to the powering down of portions thereof.